Dual port memories have independent read and write ports. For example, video dual port memories may be used to write a new frame of video data through a write port while an existing frame of video data is read through a read port. The separate read and write ports require 8-transistor (8T) bitcells. While the simultaneous read and write operations increase operating speed, the 8T bitcell structure demands die area. To increase density, pseudo dual port (PDP) memories have been developed. A PDP memory mimics the read and write ports of a dual port memory through a time multiplexing of the read and write operations within each memory clock cycle. The time multiplexing of the read/write accesses allows PDP memories to be implemented using fewer transistors, e.g., 6-transistor (6T) bitcells.
In a memory clock cycle for a PDP memory, a read operation is followed by a write operation. During the read operation, the appropriate word line is asserted to a power supply voltage VDD to retrieve the bit stored in an accessed bitcell. The asserted word line voltage switches on the access transistors to the bitcell so that the bitcell drives its corresponding bit line pair comprising a bit line and a complement bit line during the read operation. After the read operation, the selected word line turns off and the corresponding bit line and complement bit line are charged to VDD during a write precharge period. Following the precharge operation, a write driver selectively discharges either the bit line or the complement bit line to the logic low state (VSS) during a write discharge period responsive to the bit to be written into the accessed bitcell. The word line for the accessed bitcell is then asserted so that the selectively-discharged bit line pair drives the accessed memory cell to write the bit into the memory cell. After the write operation, the bit line BL and complement bit line BL_n are again precharged to prepare for the next read/write cycle. The combination of the precharge period and the discharge period for a write operation may be collectively denoted as the cleanup time, which consumes precious time in the memory cycle. The cleanup time period lengthens the write access time of the PDP memory, which limits the maximum operating frequency.
To address this speed limitation, PDP memories may be split into multiple banks to reduce the capacitive load on the bit lines so that they may be charged and discharged more rapidly. However, the use of multiple memory banks increases area and power overhead, effectively negating the size advantage of the PDP memories over true dual port memories.
Accordingly, there is a need in the art for a memory architecture that retains the area and power efficiency of a PDP memory with the speed advantage of an actual dual port memory.